1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and particularly, to a nonvolatile semiconductor memory device capable of operating in the background operation mode in which a data is externally read out in an erasure/programming operation in the interior thereof.
2. Description of the Background Art
FIG. 17 is a block diagram schematically showing a configuration of a conventional nonvolatile semiconductor memory device. In FIG. 17, the conventional nonvolatile semiconductor memory device includes a plurality of banks B#1 to B#4. Each of the banks B#1 to B#4 includes: a memory array MA having a plurality of nonvolatile memory cells arranged in rows and columns; a predecoder PD for predecoding a supplied address signal; a row decoder RD for decoding a row predecode signal supplied from the predecoder PD to select an addressed row of the memory array MA; a column decoder CD for decoding a column predecode signal supplied from the predecoder PD to generate a column select signal selecting an addressed column of the memory array MA; and a Y gate YG for selecting a corresponding column of the memory array MA according to the column select signal supplied from the column decoder CD. The banks B#1 to B#4 can be addressed independently and individually.
The nonvolatile semiconductor memory device further includes: an address buffer 1 taking in an address signal AD supplied externally therein according to a control signal CTL and generating an internal address signal to supply it to the banks B#1 to B#4; a data buffer 2 for inputting and outputting a data between the data buffer 2 and an external device; a write data buffer 4 receiving an internal write data from the data buffer 2 to store the data therein; write circuit and sense amplifier blocks 5a to 5d, provided corresponding to the respective banks B#1 to B#4, each transmitting a write data to a selected memory cell of a corresponding bank and reading a data from a selected memory cell of a corresponding bank; a bank pointer 3 for activating a bank specified by a bank address signal supplied from the address buffer 1; an erasure/programming verification circuit 6 receiving a verify data read out from the write circuit and sense amplifier blocks 5a to 5d and a write data stored in the write data buffer 4 in a write operation, and for verifying whether or not, in a selected bank, erasing has been correctly performed and whether or not, in a selected bank, data programming has been correctly performed; and internal control circuit 7 receiving a control signal CTL supplied externally, a command CMD specifying an operating mode supplied externally and a bank address signal supplied from the bank pointer 3, and controlling operations of the data buffer 2 and the bank pointer 3 but as well as setting an internal address signal generated from the address buffer 1 in an internal operation.
The control signal includes a chip enable signal /CE, a write enable signal /WE and an output enable signal /OE. The command CMD specifies a data erase mode, a data write mode and the like, and is supplied through a data bus.
The nonvolatile semiconductor memory device shown in FIG. 17 is a flash memory in which one memory cell is formed of one floating gate field effect transistor. Data storage in a memory cell is achieved by injection/extraction of electric charges to/from the floating gate of a floating gate field effect transistor to change a threshold voltage thereof.
It has been established that an access time for a data read operation ranges from 50 nsec (nanoseconds) to 200 nsec and on the other hand, an erasure/programming operation requires to change a threshold voltage of a memory cell transistor (in a unit of a memory block) and therefore, it takes a relatively long time ranging from 2 xcexcs (microseconds) to 5 s (seconds). In the prior art, it is impossible to read out a data in the chip during an internal operation in which the erasure/programming operation is performed. In a case where a plurality of banks B#1 to B#4 are provided as shown in FIG. 17, however, while an internal operation for programming/erasing is performed on a bank, can be accessed for data reading from another bank. An operation in which while an internal operation is actually performed in one bank, a data can be read out from another bank, is called a BGO (background operation) function. In order to realize this BGO function, an external operation address signal and an internal operation address signal are generated from the address buffer and further, the write circuit and sense amplifier blocks 5a to 5d are provided corresponding to the respective banks B#1 to B#4. According to an operating mode, the write circuit and sense amplifier blocks 5a to 5d are coupled to either the erasure/programming verification circuit 6 or the data buffer 2. The selective connection is performed under control of the internal control circuit 7 according to a bank specifying signal supplied from the bank pointer 3.
FIG. 18 is a circuit diagram representing a construction of a sense amplifier included in each of the write circuit and sense amplifier blocks 5a to 5d shown FIG. 17. In FIG. 18, the sense amplifier includes: a current sense circuit 901, activated when a sense amplifier enable signal ZSE is activated, for amplifying a data transmitted through an internal data transmission line 900 from the Y gate YG; an N channel MOS transistor 902, made conductive when the sense amplifier enable signal ZSE is deactivated, for precharging a node 907 to the ground voltage level; two cascaded CMOS inverters 903 and 904 amplifying a signal on the node 907; an internal output circuit 905, activated when an external read output enable signal EXRDE is activated, for buffering (amplifying) a signal supplied from the CMOS inverter 904 to transmit the buffered signal to the data buffer 2; and an internal output circuit 906, activated when a verify output enable signal VFRDE is activated, for buffering (amplifying) an output signal of the CMOS inverter 904 to supply the output signal to the erasure/programming verification circuit 6.
The current sense circuit 901 includes: a P channel MOS transistor PQ1, made conductive when the sense amplifier enable signal ZSE is activated, for supplying a current to the node 907; a P channel MOS transistor PQ2 made conductive when the sense amplifier enable signal ZSE is activated and transmitting a power supply voltage when made conductive; an N channel MOS transistor NQ3 connected between the MOS transistor PQ2 and the ground node, and receiving the sense amplifier enable signal ZSE at a gate thereof; an N channel MOS transistor NQ 1 connected between the node 907 and the internal data line 900, and coupled with drains of the MOS transistors PQ2 and PQ3 at a gate thereof; and an N channel MOS transistor NQ2 connected in parallel to the MOS transistor NQ3, and connected to the internal data transmission line 900 at a gate thereof.
The first internal output circuit 905 includes: P channel MOS transistors PQ3 and PQ4 connected serially between a power supply node and a first output node; and N channel MOS transistors NQ4 and NQ5 connected serially between the first output node and a ground node. An output signal of the CMOS inverter 904 is supplied to the gates of the MOS transistors PQ3 and NQ5, and the external read output enable signal EXRDE is supplied to the gate of the MOS transistor PQ4 through an inverter. Further, the external read output enable signal EXRDE is supplied to the gate of the MOS transistor NQ4.
The second internal output circuit 906 includes: P channel MOS transistors PQ5 and PQ6 connected serially between a power supply node and a second output node; and N channel MOS transistors NQ6 and NQ7 connected serially between the second output node and a ground node. An output signal of the CMOS inverter 904 is supplied to the gates of the MOS transistors PQ5 and NQ7. The verify output enable signal VFRDE is supplied to the gate of the MOS transistor PQ6 through an inverter and further, the verify output enable signal VFRDE is supplied to the gate of the MOS transistor NQ6.
The internal data transmission line 900 is coupled to a selected column of a corresponding memory array through the Y gate YG. When the sense amplifier enable signal ZSE is inactive at H level, the MOS transistor PQ1 and PQ2 are turned off, while the MOS transistor NQ3 is turned on in the current sense circuit 901. Therefore, the gate of the MOS transistor NQ1 is coupled to a ground node through the MOS transistor NQ3, and the MOS transistor NQ1 is turned off to disconnect the node 907 and the internal data transmission line 900 from each other. Further, the MOS transistor 902 is turned on and the node 907 is fixed at the ground voltage level.
When the sense amplifier enable signal ZSE goes to L level of the active state, the MOS transistors PQ1 and PQ2 are turned on, while the MOS transistor NQ3 is turned off. Further, the MOS transistor 902 is turned off. Therefore, the node 907 is charged by the MOS transistor PQ1 toward the power supply voltage level. Further, the MOS transistor NQ1 receives the power supply voltage at the gate thereof through the MOS transistor PQ2, to turn on for coupling the node 907 with the internal data transmission line 900. Therefore, a voltage lower than the power supply voltage by a threshold voltage of the MOS transistor NQ1 is transmitted to the internal data transmission line 905 through the MOS transistor NQ1. When a threshold voltage of a memory cell on a column selected by the Y gate YG is low, a current flows through the memory cell and a voltage level on the internal transmission line 900 decreases and the MOS transistor NQ2 is turned off, a current flows from the MOS transistors PQ1 and NQ1 to the internal data transmission line 900 to reduce a voltage level of the node 907.
On the other hand, when a threshold voltage of a memory cell selected by the Y gate YG is high, no current flows through the selected memory cell and the internal data transmission line 900 goes to a voltage level charged by the MOS transistors PQ1 and NQ1. Accordingly, the MOS transistor NQ2 is turned on to discharge the gate of the MOS transistor NQ1 to the ground voltage level. Therefore, the MOS transistor NQ1 is turned off and the node 907 maintains H level charged by the MOS transistor PQ1. A voltage level of the node 907 is amplified by the CMOS inverters 903 and 904 and the amplified voltage is transmitted to the internal output circuits 905 and 906.
In the internal output circuit 905, when the external read output enable signal EXRDE is inactive at L level, the MOS transistors PQ4 and NQ4 are off and the internal output circuit 905 is in an output high impedance state. On the other hand, when the external read output signal EXRDE is activated at H level, the MOS transistors PQ4 and NQ4 are turned on and the internal output circuit 905 inverts the signal supplied from the CMOS inverter 904 and transmits the inverted signal to the data buffer 2. The data buffer 2 is activated under control of the internal control circuit 7 shown in FIG. 17 and buffers a data supplied from the internal output circuit 905 to output the buffered data to an outside.
When the verify output enable signal VFRDE is inactive at L level, the MOS transistors PQ6 and NQ6 in the internal output circuits 906 are off and the internal output circuit 906 is in the output high impedance state. When the verify output enable signal VFRED is activated at H level, the MOS transistors PQ6 and NQ6 are turned on and a signal from the CMOS inverter 904 is buffered and supplied to the erasure/programming verification circuit 6.
The erasure/programming verification circuit 6 identify, in an erasure operating mode, whether or not a signal supplied from the internal output circuit 906 is at a logical level corresponding to the erased state and determines whether or not erasing has been correctly effected. On the other hand, the erasure/programming verification circuit 6 identifies, in a program mode, whether or not a data supplied from the internal output circuit 906 is at a logic level corresponding a write data and determines whether or not data writing has been correctly effected. The output enable signals EXRDE and VFRDE are selectively activated by the internal control circuit 7 according to whether an internal operation or an external operation is effected, based on a signal generated from the bank pointer.
FIG. 19 is a circuit diagram representing a configuration of a Y gate shown in FIG. 17. FIG. 19 shows a portion including the Y gate for selecting a memory cell of one bit from memory cells of 8 bits. In FIG. 19, the Y gate YG includes: column select gates TR0 to TR3 each formed of an N channel MOS transistor, and provided corresponding to respective internal data lines DL0 to DL3, and made conductive when column select signals CAL0 to CAL3 are selected, respectively, and column select gates TR4 to TR7 formed of N channel MOS transistors, provided corresponding to respective internal data lines DL4 to DL7, and made conductive when column select signals CAL0 to CAL3 are selected, respectively.
The internal data lines DL0 to DL7 are, for example, bit lines in the memory array MA and a column of memory cells are connected to each of the lines DL0 to DL7. A column (an internal data line) is selected according to a column address in a set of the internal data lines DL0 to DL3 and in a set of the internal data lines DL4 to DL7 by the column select gates TR0 to TR 3 and TR4 to TR7, and the selected columns are coupled to respective global data lines GDL0 and GDL1.
The Y gate YG further includes block select gates TR8 and TR9 formed of N channel MOS transistors, provided corresponding to the global data lines GDL0 and GDL1, and made conductive when respective column block select signals CAU0 and CAU1 are activated to couple the corresponding global data lines GDL0 and GDL1 to the internal transmission line 900.
In the Y gate YG shown in FIG. 19, a total of 2 bits composed of one bit from the internal data line DL0 to DL3 and one bit from the internal data line DL4 to DL7 are selected according to the column select signal CAL0 to CAL3 and the two bits are transmitted to the respective global data lines GDL0 to GDL1. Then, one of the global lines GDL0 and GDL1 is coupled to the sense amplifier circuit through the internal transmission line 900 according to the column block select signals CAU0 and CAU1. The internal transmission line 900 is also coupled to the write circuit included in a corresponding write circuit and sense amplifier block 5 (5a to 5d), and data reading and data writing are effected through the Y gate YG.
It should be appreciated that the memory array MA is divided into a plurality of blocks and a plurality of bits are read out in parallel. In FIG. 19, although a configuration is shown in which a memory cell of 1 bit is simply selected from memory cells of 8 bits, a scale of the Y gate YG is expanded, proportional to the number of internal data lines included in one column block and the number of column blocks.
FIG. 20 is a circuit diagram representing an example of configuration of a column decoder shown in FIG. 17. In FIG. 20, the column decoder CD includes: an OR circuit 910 receiving an external read bank specifying signal EBP_X and an internal operation bank specifying signal IBP_X to generate a bank specifying signal BP_X; inverters 911 to 913 inverting predecode signals (or address signal bits) A0 to A2 to generate complimentary predecode signal /A0 to /A2; and column decode circuits 914 to 919, enabled when the bank specifying signal BP_X is activated, for performing a decode operation.
The column decode circuit 914 receives the predecode signal /A0 and the bank specifying signal BP_X to generate the column select signal CAL0. The column decode circuit 915 receives the predecode signals A0 and /A1, and the bank specifying signal BP_X to generate the column signal CAL1. The column decode circuit 916 receives the predecode signals /A0 and A1, and the bank specifying signal BP_X to generate the column select signal CAL2. The column decode circuit 917 receives the predecode signals A0 and A1, and the bank specifying signal BP_X to generate the column select signal CAL3. The column decode circuit 918 receives the predecode signal /A2 and the bank specifying signal BP_X to generate the column block select signal CAU0. The column decode circuit 919 receives the predecode signal A2 and the bank specifying signal BP_X to generate the column block select signal CAU1.
Level converters 920 are provided corresponding to the respective column select signals CAL0 to CAL3, and to the respective column block select signals CAU0 to CAU1. The level converters 920 each receive a high voltage VP as one operating power supply voltage and converts a voltage level of a corresponding signal from a normal operation power supply voltage to a high voltage VP while maintaining a logical level thereof. When a programming operation is performed, a level conversion of a selected column select signal is performed using level converter 920 in order that a high programming voltage is transmitted onto a selected column through a column select gate formed of an N channel MOS transistor as shown in FIG. 19.
The predecode signals A0 to A2 are supplied from the predecoder PD shown in FIG. 17. The column decode circuits 914 to 919 each are an AND type decode circuit and enabled when the bank specifying signal BP_X is activated at H level, to perform a decode operation. One of the column select signals CAL0 to CAL3 and one of the column block select signals CAU0 to CAU1 are driven to a selected state (H level) according to the predecode signals A0 to A2. With such driving to the selected state, one column (of memory cells) is selected in the memory array MA.
It should be appreciated that the predecode signals A0 to A2, and /A0 to /A2 may be address signal bits.
In the nonvolatile semiconductor memory device as shown in FIG. 17, a data can be read out from a bank through accessing that bank while an internal operation for erasing/programming is performed on another bank. It is necessary, however, to provide a write circuit and a sense amplifier circuit for each bank in order to realize the background operation (BGO) function. Especially, in a sense amplifier as shown in FIG. 18, output circuits are required to be provided for external data outputting and for an internal operation (for verifying), separately, and there arises a problem that an occupying area of a sense amplifier is larger. Specifically, when the number of banks is increased in order to improve an operating efficiency of the nonvolatile semiconductor memory device, the number of sense amplifiers increases proportionally, thereby resulting in great increase in chip occupied area.
It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of suppressing increase in chip area with degradation of a background operation function even when the number of banks increases.
It is another object of the present invention to provide a flash memory with a background operation function being capable of increasing the number of banks while suppressing increase in number of internal data read circuits.
A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a plurality of memory banks each having a plurality of nonvolatile memory cells; at least one sense amplifier for read operation, provided corresponding to a prescribed number of memory banks of the plurality of memory banks, for outputting externally a data read out from a corresponding bank through a buffer circuit; and an sense amplifier for internal operation, provided corresponding to the plurality of memory banks and separately from the sense amplifier for read operation, for reading out a memory cell data from a corresponding memory bank for a prescribed internal operation.
A nonvolatile semiconductor memory device according to another aspect of the present invention includes: a memory array having a plurality of nonvolatile memory cells arranged in a matrix of rows and columns; an external sense amplifier circuit for reading out a data on a selected memory cell of the memory array to an outside; an sense amplifier for internal operation, provided separately from the external sense amplifier circuit, for reading out a data from a selected memory cell of the memory array for a prescribed internal operation; and a select circuit for coupling the selected memory cell of the memory array to the external sense amplifier circuit and the sense amplifier for internal operation through different paths.
A nonvolatile semiconductor memory device according to still another aspect of the present invention is a nonvolatile semiconductor memory device with a background operation function, in which a plurality of internal data read paths are provided extending from one memory cell array.
By providing a sense read circuit for external reading corresponding to a prescribed number of memory banks, it is unnecessary to provide external read sense amplifiers corresponding to respective memory banks, thereby enabling a chip area to decrease.
By connecting a sense read circuit for external reading and a sense read circuit for an internal operation to a bank through different paths, efficient placement of the sense read circuit for an internal operation can be realized, thereby improving a layout efficiency and reducing a chip area.
Further, by providing a plurality of output paths for a memory array, an internal operation amplifier and an external read sense amplifier can be separately disposed in an efficient way and therefore, a chip area can be efficiently utilized to decrease a chip area.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.